Logic Gates — Truth Tables and Combinations

Why logic gates are exam gold

Class 12 Semiconductors closes with logic gates — and this is where the chapter pays off. The questions are short, scoring, and almost always direct truth-table or boolean-algebra problems. CBSE typically asks one 2-mark or 3-mark question on logic gates every board exam. JEE Main and NEET treat them as easy MCQs.

We will work through every gate, what its truth table looks like, how to combine gates to make new ones, and the kind of trap questions examiners reuse.

The good news: the entire topic has only seven gates and three rules. Learn them once and you score 100% in this section forever.

Key Terms & Definitions

Logic gate — an electronic circuit that produces a single binary output (0 or 1) for a given combination of binary inputs.

Truth table — a list of all possible input combinations and the corresponding outputs. For two inputs, four rows; for three inputs, eight rows.

Boolean algebra — the rules used to simplify logical expressions. Symbols: $A \cdot B$ for AND, $A + B$ for OR, $\bar{A}$ for NOT.

Universal gate — a gate from which all other gates can be built. NAND and NOR are both universal.

The Seven Gates

NOT (inverter)

One input, one output. Output is the negation of input.

A	$\bar{A}$
0	1
1	0

AND

Output is 1 only if all inputs are 1.

A	B	A·B
0	0	0
0	1	0
1	0	0
1	1	1

OR

Output is 1 if at least one input is 1.

A	B	A+B
0	0	0
0	1	1
1	0	1
1	1	1

NAND (NOT-AND)

Output is the inverse of AND. Universal gate.

A	B	$\overline{A \cdot B}$
0	0	1
0	1	1
1	0	1
1	1	0

NOR (NOT-OR)

Output is the inverse of OR. Universal gate.

A	B	$\overline{A + B}$
0	0	1
0	1	0
1	0	0
1	1	0

XOR (Exclusive OR)

Output is 1 if exactly one input is 1.

A	B	A⊕B
0	0	0
0	1	1
1	0	1
1	1	0

XNOR

Inverse of XOR — output is 1 when inputs match.

Building Gates from NAND

$\text{NOT}(A) = \overline{A \cdot A}$ (NAND with both inputs tied)

$\text{AND}(A,B) = \overline{\overline{A \cdot B}}$ (NAND followed by NOT-via-NAND)

$\text{OR}(A,B) = \overline{\bar{A} \cdot \bar{B}}$ (use De Morgan: each input inverted, then NAND)

This means a single type of NAND chip can implement any digital circuit. NOR can do the same. JEE often asks “express OR using only NAND” — drill the steps above.

Worked Examples

Easy (CBSE Class 12)

Example 1. Two inputs $A = 1, B = 0$ enter a NAND gate. Output?

$A \cdot B = 0$ , so $\overline{A \cdot B} = 1$ . Output is 1.

Medium (JEE Main)

Example 2. Show that $A + \bar{A}B = A + B$ .

Truth table approach: tabulate $A, B, \bar{A}, \bar{A}B, A + \bar{A}B$ for all four combinations.

A	B	$\bar{A}$	$\bar{A}B$	$A + \bar{A}B$	$A+B$
0	0	1	0	0	0
0	1	1	1	1	1
1	0	0	0	1	1
1	1	0	0	1	1

Columns 5 and 6 match — the identity holds.

Hard (JEE Advanced)

Example 3. A circuit takes inputs $A$ and $B$ through two NAND gates and produces output $Y = \overline{A \cdot B} \cdot \overline{A + B}$ . Build the truth table and identify the gate.

A	B	$\overline{A \cdot B}$	$\overline{A + B}$	$Y$
0	0	1	1	1
0	1	1	0	0
1	0	1	0	0
1	1	0	0	0

This matches NOR.

Exam-Specific Tips

CBSE marking: drawing the gate symbol AND writing the truth table together earns full marks. Just one of them earns half. Always do both.

For JEE, learn De Morgan’s laws by heart: $\overline{A + B} = \bar{A} \cdot \bar{B}$ and $\overline{A \cdot B} = \bar{A} + \bar{B}$ . They appear in nearly every boolean simplification question.

NEET tends to ask “which gate gives output 1 when both inputs are 0?” Answer: NOR. Memorise the corner cases of each truth table.

Common Mistakes to Avoid

Confusing NAND and NOR. NAND is high except when both inputs are 1; NOR is high only when both inputs are 0. Different corner cases.

Forgetting that XOR is true only when inputs differ. Students sometimes treat XOR like OR.

Drawing the wrong symbol. The bubble at the output of NAND/NOR is what makes them inverted versions. Skip the bubble in a CBSE answer and you lose the mark.

Mixing up $A + B$ (boolean OR, gives 1 if any input is 1) with arithmetic addition (which would give 2 for $1+1$ ). In digital logic, $1 + 1 = 1$ .

Applying De Morgan’s law incorrectly — flipping $\cdot$ to $+$ but forgetting to invert each individual variable. Both swaps must happen together.

Practice Questions

Q1. Truth table of $Y = A \cdot \bar{B}$ .

$Y = 1$ only when $A = 1, B = 0$ . Otherwise $Y = 0$ .

Q2. Construct AND using only NOR gates.

$A \cdot B = \overline{\overline{A \cdot B}} = \overline{\bar A + \bar B}$ . Use NOR on $\bar A, \bar B$ . To get $\bar A$ via NOR: tie inputs $A$ to both pins of a NOR gate.

Q3. Output of XOR with inputs $A = 1, B = 1$ .

$1 \oplus 1 = 0$ .

Q4. Simplify $A \cdot (\bar A + B)$ .

$A \cdot \bar A + A \cdot B = 0 + A \cdot B = A \cdot B$ .

Q5. Truth table of XOR is the same as which combination?

$A \oplus B = A \cdot \bar B + \bar A \cdot B$ .

Q6. Why is NAND universal?

Because NOT, AND, and OR can each be built from NAND alone.

Q7. Output of NOR with $A = 0, B = 0$ ?

$1$ .

Q8. Apply De Morgan’s law to $\overline{A \cdot B \cdot C}$ .

$\bar A + \bar B + \bar C$ .

FAQs

Q. Are logic gates only theoretical?

No — they are real silicon circuits inside every CPU. The textbook describes idealised behaviour; real gates have propagation delay and limits on input voltage.

Q. Why two universal gates (NAND and NOR)?

Either alone is enough. Engineers prefer NAND because it is slightly cheaper and faster in CMOS technology, but in board-exam terms either is fine.

Q. What is the difference between combinational and sequential circuits?

Combinational depends only on current inputs (gates we covered). Sequential includes memory — flip-flops, latches. CBSE Class 12 deals only with combinational.

Q. How do truth tables help in real design?

Designers start with the desired truth table, then use boolean simplification (Karnaugh maps, beyond syllabus) to find the smallest gate combination.

Q. Are XOR and XNOR universal?

No. They cannot independently build all other gates because they lack the ability to express AND/OR purely.